1. Field of the Invention
The present invention relates to a clock recovery circuit which is incorporated in a receiving device for digital television broadcasts using a VSB modulation method.
2. Description of the Related Art
As a clock recovery circuit according to the prior art, for example, there is a per se known type “VSB modulation used for terrestrial and cable broadcasts” described in the publication, IEEE Trans. Consumer Electronics, Vol. 41, No. 3, pp. 367-381, August 1995.
FIG. 1 is a structural view showing the above identified clock recovery circuit including A/D converter. In this clock recovery circuit, an A/D converter 1 inputs a VSB signal which has been converted to baseband, and converts it to digital data using a synchronous clock signal. A correlation filter 2 detects data breaks of fixed lengths in the data series which is inputted from the A/D converter 1. A segment integrator 3 inputs the output data from the correlation filter 2, and performs integration for each of 832 symbols. A segment detector 4 detects data segment sync which exist for each of the 832 symbols. A phase error detector 5 detects the phase error using data segment sync, and outputs a phase error signal. A loop filter 6 smoothes the phase error signal, and controls a reference clock of receiving device generator (VCXO) 7 using this phase error signal. This reference clock signal generator 7 comprises a voltage control oscillator which employs a crystal oscillator. The reference clock generator 7 generates a synchronous reference clock signal which is phase-controlled, and supplies it to the A/D converter 1 as a sampling clock signal.
In the clock recovery circuit, the phase error between the symbol clock of the received VSB signal and the reference clock of the receiving device is detected using data segment sync which exist for each of the 832 symbols. Due to this, it becomes impossible to perform high speed tracking of the synchronous clock signal when the received signal is varying over time.
Furthermore, when performing signal reception in conditions of lower C/N ratio, or when the influence of multi-pass distortion is being experienced, data segment sync undesirably becomes distorted, and correct detection of the phase error of the synchronous clock signal becomes impossible. In this case, it becomes impossible to regenerate an accurate clock signal.